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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems is a peer-reviewed journal published by IEEE, covering VLSI and FPGA Design Techniques, VLSI and Analog Circuit Testing, Low-power high-performance VLSI design. Over its lifetime it has published 9,966 papers, which have received 271,747 citations.
| Publisher | IEEE |
|---|---|
| Reference style | Numbered (IEEE) Numbered — [1], [2] in the text [1] A. Smith, B. Jones, and C. Lee, "A representative article title," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 3, pp. 45–58, 2023.
Formats any DOI in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems style. No sign-up. |
| Abbreviation (ISO-4) | TCAD |
| Publishes research in | VLSI and FPGA Design Techniques VLSI and Analog Circuit Testing Low-power high-performance VLSI design Embedded Systems Design Techniques Parallel Computing and Optimization Techniques |
| ISSN | 0278-0070 |
| Citation impact (2-yr) | 2.51 |
| h-index | 189 |
| i10-index | 5,016 |
| Top institutions publishing here | Intel (United States) |
| Journal website | ieee-ceda.org |
| You get | A submission-ready PDF and the editable LaTeX source — ready to submit. |
Citations each year’s papers have accumulated so far — the most recent years are still building up.
Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The transient portion of the response is approximated by matching the initial boundary conditions and the first 2q-1 moments of the exact response to a…
The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data. This type of intelligent computing poses a set of constraints, including real-time operation, low-power consumption and scalability, which require a radical departure from conventional system design. Brain-inspired architectures offer tremendous promise in…
This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining…
In this paper, we introduce PVL, an algorithm for computing the Pade approximation of Laplace-domain transfer functions of large linear networks via a Lanczos process. The PVL algorithm has significantly superior numerical stability, while retaining the same efficiency as algorithms that compute the Pade approximation directly through moment matching, such as AWE and its derivatives.…
Partitioning of circuit netlists in VLSI design is considered. It is shown that the second smallest eigenvalue of a matrix derived from the netlist gives a provably good approximation of the optimal ratio cut partition cost. It is also demonstrated that fast Lanczos-type methods for the sparse symmetric eigenvalue problem are a robust basis for…
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