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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Template

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About the IEEE Transactions on Very Large Scale Integration (VLSI) Systems format

IEEE Transactions on Very Large Scale Integration (VLSI) Systems is a peer-reviewed journal published by IEEE, covering Low-power high-performance VLSI design, Parallel Computing and Optimization Techniques, Embedded Systems Design Techniques. Over its lifetime it has published 7,648 papers, which have received 172,781 citations.

PublisherIEEE
Reference styleNumbered (IEEE)
Numbered — [1], [2] in the text
[1] A. Smith, B. Jones, and C. Lee, "A representative article title," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 45–58, 2023.

Formats any DOI in IEEE Transactions on Very Large Scale Integration (VLSI) Systems style. No sign-up.

Abbreviation (ISO-4)TVLSI
Publishes research inLow-power high-performance VLSI design Parallel Computing and Optimization Techniques Embedded Systems Design Techniques VLSI and Analog Circuit Testing Interconnection Networks and Systems
ISSN1063-8210
Citation impact (2-yr)2.13
h-index146
i10-index3,705
Top institutions publishing hereIntel (United States)
Journal websiteieeexplore.ieee.org
You getA submission-ready PDF and the editable LaTeX source — ready to submit.

Papers published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems per year

409
2014
326
2015
321
2016
390
2017
339
2018
320
2019
257
2020
224
2021
229
2022
272
2023
318
2024
368
2025

Citation impact of IEEE Transactions on Very Large Scale Integration (VLSI) Systems by publication year

8.5K
2014
6K
2015
6.1K
2016
7.1K
2017
7.3K
2018
7.4K
2019
4.4K
2020
3.2K
2021
2.9K
2022
2.5K
2023
1.3K
2024
484
2025

Citations each year’s papers have accumulated so far — the most recent years are still building up.

Most-cited papers in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A survey of design techniques for system-level dynamic power management

Luca Benini, Alessandro Bogliolo, G. De Micheli · 1 Jun 2000

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components…

1,232 citations Cite SaveGo to paper →
HotSpot: a compact thermal modeling methodology for early-stage VLSI design

Wei Huang, Sudeep Ghosh, S. Velusamy et al. · 1 May 2006

This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during…

1,094 citations Cite SaveGo to paper →
Extracting secret keys from integrated circuits

Daihyun Lim, J.W. Lee, Blaise Gassend et al. · 1 Oct 2005

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires…

1,038 citations Cite SaveGo to paper →
Power analysis of embedded software: a first step towards software power minimization

Vivek Tiwari, Sharad Malik, A. Wolfe · 1 Dec 1994

Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design-the circuit or gate level.…

Bus-invert coding for low-power I/O

Mircea R. Stan, Wayne Burleson · 1 Mar 1995

Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances.…

IEEE Transactions on Very Large Scale Integration (VLSI) Systems template — frequently asked questions

How do I write a paper in the IEEE Transactions on Very Large Scale Integration (VLSI) Systems format?
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What reference style does IEEE Transactions on Very Large Scale Integration (VLSI) Systems use?
IEEE Transactions on Very Large Scale Integration (VLSI) Systems uses Numbered (IEEE) references, shown as numbered [1], [2] markers in the text. DocuGuru formats every in-text citation and the reference list in this exact style automatically. A reference appears like this: [1] A. Smith, B. Jones, and C. Lee, "A representative article title," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 45–58, 2023.
Do I need to know LaTeX to submit to IEEE Transactions on Very Large Scale Integration (VLSI) Systems?
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Who publishes IEEE Transactions on Very Large Scale Integration (VLSI) Systems?
IEEE Transactions on Very Large Scale Integration (VLSI) Systems is a engineering and computer science journal published by IEEE. DocuGuru's IEEE Transactions on Very Large Scale Integration (VLSI) Systems template matches IEEE's official submission format.
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