Write in a clean editor, then format for IEEE Micro in one click — DocuGuru applies the official IEEE template with numbered references and exports a submission-ready PDF plus the editable LaTeX source. Free to start.
IEEE Micro is a peer-reviewed journal published by IEEE, covering Parallel Computing and Optimization Techniques, Diverse Scientific and Economic Studies, Human auditory perception and evaluation. Over its lifetime it has published 5,181 papers, which have received 97,359 citations.
| Publisher | IEEE |
|---|---|
| Reference style | Numbered (IEEE) Numbered — [1], [2] in the text [1] A. Smith, B. Jones, and C. Lee, "A representative article title," IEEE Micro, vol. 12, no. 3, pp. 45–58, 2023.
Formats any DOI in IEEE Micro style. No sign-up. |
| Publishes research in | Parallel Computing and Optimization Techniques Diverse Scientific and Economic Studies Human auditory perception and evaluation Embedded Systems Design Techniques Interconnection Networks and Systems |
| ISSN | 0272-1732 |
| Citation impact (2-yr) | 1.6 |
| h-index | 138 |
| i10-index | 1,190 |
| Top institutions publishing here | Intel (United States) |
| Journal website | www.computer.org |
| You get | A submission-ready PDF and the editable LaTeX source — ready to submit. |
Citations each year’s papers have accumulated so far — the most recent years are still building up.
Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally…
The Myrinet local area network employs the same technology used for packet communication and switching within massively parallel processors. In realizing this distributed MPP network, we developed specialized communication channels, cut-through switches, host interfaces, and software. To our knowledge, Myrinet demonstrates the highest performance per unit cost of any current LAN.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
To enable flexible, programmable graphics and high-performance computing, NVIDIA has developed the Tesla scalable unified graphics and parallel computing architecture. Its scalable parallel array of processors is massively multithreaded and programmable in C or via graphics APIs.
As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article…
Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: 1) reduce gate delay by 30%, resulting in an increase in operating frequency of about 43%; 2) double transistor density; and 3) reduce energy per transition by about 65%, saving 50%…
IEEE Transactions on Nuclear Science
IEEE Transactions on Power Electronics
IEEE Transactions on Radar Systems
IEEE Transactions on Services Computing
IEEE Transactions on Software Engineering
IEEE Transactions on Terahertz Science and Technology
Journal of Electrochemical Energy Conversion and Storage
Journal of Fluids Engineering
