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IEEE Embedded Systems Letters is a peer-reviewed journal published by IEEE, covering Parallel Computing and Optimization Techniques, Embedded Systems Design Techniques, Diverse Scientific and Economic Studies. Over its lifetime it has published 1,244 papers, which have received 8,661 citations.
| Publisher | IEEE |
|---|---|
| Reference style | Numbered (IEEE) Numbered — [1], [2] in the text [1] A. Smith, B. Jones, and C. Lee, "A representative article title," IEEE Embedded Systems Letters, vol. 12, no. 3, pp. 45–58, 2023.
Formats any DOI in IEEE Embedded Systems Letters style. No sign-up. |
| Abbreviation (ISO-4) | ESL |
| Publishes research in | Parallel Computing and Optimization Techniques Embedded Systems Design Techniques Diverse Scientific and Economic Studies Ferroelectric and Negative Capacitance Devices Real-Time Systems Scheduling |
| ISSN | 1943-0663 |
| Citation impact (2-yr) | 1.39 |
| h-index | 42 |
| i10-index | 228 |
| Top institutions publishing here | University of California, Irvine |
| Journal website | ieeexplore.ieee.org |
| You get | A submission-ready PDF and the editable LaTeX source — ready to submit. |
Citations each year’s papers have accumulated so far — the most recent years are still building up.
A key challenge to the future of energy-harvesting systems is the discontinuous power supply that is often generated. We propose a new approach, Hibernus, which enables computation to be sustained during intermittent supply. The approach has a low energy and time overhead which is achieved by reactively hibernating: saving system state only once, when power…
Approximate multiplication is a common operation used in approximate computing methods for high performance and low power computing. Power-efficient circuits for approximate multiplication can be realized with an approximate 4-2 compressor. This letter presents a novel design that uses a modification of a previous approximate 4-2 compressor design and adds an error recovery module. The…
High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest…
<para> Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard…
Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 (see Ref [1] Kahng etal., Proc. DATE, 2009, pp. 423-428) is a widely adopted NoC power and area estimation tool, but its estimation models can have large errors (up to 185%) versus actual implementations. We present ORION3.0, an open-source tool whose parametric and nonparametric modeling methodologies…
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