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ACM Transactions on Architecture and Code Optimization is a peer-reviewed journal published by ACM, covering Parallel Computing and Optimization Techniques, Advanced Data Storage Technologies, Interconnection Networks and Systems. Over its lifetime it has published 1,385 papers, which have received 19,012 citations.
| Publisher | ACM |
|---|---|
| Reference style | Numbered (ACM) Numbered — [1], [2] in the text [1] Ada Smith, Ben Jones, and Cara Lee. 2023. A representative article title. ACM Transactions on Architecture and Code Optimization 12, 3, Article 45 (2023).
Formats any DOI in ACM Transactions on Architecture and Code Optimization style. No sign-up. |
| Publishes research in | Parallel Computing and Optimization Techniques Advanced Data Storage Technologies Interconnection Networks and Systems Cloud Computing and Resource Management Embedded Systems Design Techniques |
| ISSN | 1544-3566 |
| Citation impact (2-yr) | 1.78 |
| h-index | 56 |
| i10-index | 510 |
| Open access | Yes |
| Top institutions publishing here | Huazhong University of Science and Technology |
| Journal website | dl.acm.org |
| You get | A submission-ready PDF and the editable LaTeX source — ready to submit. |
Citations each year’s papers have accumulated so far — the most recent years are still building up.
With cooling costs rising exponentially, designing cooling solutions for worst-case power dissipation is prohibitively expensive. Chips that can autonomously modify their execution and power-dissipation characteristics permit the use of lower-cost cooling solutions while still guaranteeing safe temperature regulation. Evaluating techniques for this dynamic thermal management (DTM), however, requires a thermal model that is practical for…
Historically, server designers have opted for simple memory systems by picking one of a few commoditized DDR memory products. We are already witnessing a major upheaval in the off-chip memory hierarchy, with the introduction of many new memory products—buffer-on-board, LRDIMM, HMC, HBM, and NVMs, to name a few. Given the plethora of choices, it is…
This article addresses the compilation of a sequential program for parallel execution on a modern GPU. To this end, we present a novel source-to-source compiler called PPCG. PPCG singles out for its ability to accelerate computations from any static control loop nest, generating multiple CUDA kernels when necessary. We introduce a multilevel tiling strategy and…
Large core counts and complex cache hierarchies are increasing the burden placed on commonly used simulation and modeling techniques. Although analytical models provide fast results, they do not apply to complex, many-core shared-memory systems. In contrast, detailed cycle-level simulation can be accurate but also tends to be slow, which limits the number of configurations that…
This article introduces McPAT, an integrated power, area, and timing modeling framework that supports comprehensive design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. At microarchitectural level, McPAT includes models for the fundamental components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches,…
