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ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter is a peer-reviewed journal published by ACM, covering Parallel Computing and Optimization Techniques, Embedded Systems Design Techniques, Distributed and Parallel Computing Systems.
| Publisher | ACM |
|---|---|
| Reference style | Numbered (ACM) Numbered — [1], [2] in the text [1] Ada Smith, Ben Jones, and Cara Lee. 2023. A representative article title. ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter 12, 3, Article 45 (2023).
Formats any DOI in ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter style. No sign-up. |
| Publishes research in | Parallel Computing and Optimization Techniques Embedded Systems Design Techniques Distributed and Parallel Computing Systems Logic, programming, and type systems Modular Robots and Swarm Intelligence |
| ISSN | 0163-5751 |
| h-index | 28 |
| i10-index | 85 |
| Total citations | 4,844 |
| Top institutions publishing here | IBM (United States) |
| Journal website | portal.acm.org |
| You get | A submission-ready PDF and the editable LaTeX source — ready to submit. |
Citations each year’s papers have accumulated so far — the most recent years are still building up.
article Effective compiler support for predicated execution using the hyperblock Share on Authors: Scott A. Mahlke View Profile , David C. Lin View Profile , William Y. Chen View Profile , Richard E. Hank View Profile , Roger A. Bringmann View Profile Authors Info & Claims ACM SIGMICRO NewsletterVolume 23Issue 1-2Dec. 1992 pp 45–54https://doi.org/10.1145/144965.144998Online:10 December…
Horizontal architectures are attractive for cost-effective, high performance scientific computing. They are, however, very difficult to schedule. Consequently, it is difficult to develop compilers that can generate efficient code for such architectures. The polycyclic architecture has been developed specifically to make the task of scheduling easy. As a result, it has been possible to develop…
the cache miss ratio for the scalar execution of the matrix multiply for matrix sizes of 100 x 100. For comparison purposes the corresponding vector execution is also shown. The results were obtained using trace driven simulation of 2 4 Kbyte cache with block sizes of 8, 16,32 and 64 bytes. The traces are from…
The difference in code size between RISC and CISC processors appears to be a significant factor limiting the use of RISC architectures in embedded systems. Fortunately, RISC programs can be effectively compressed.
An ideal VLIW architecture requires a large multiport register file that is currently not realizable in practice. We analyze a Limited Connectivity VLIW architecture as a realizable alternative that limits the number of ports. We present a fine-grain code partitioning method for this model. The partitioning scheme was applied to a number of standard benchmarks…
ACM Transactions on Internet of Things
ACM Transactions on Modeling and Computer Simulation
ACM Transactions on Probabilistic Machine Learning
ACM Transactions on Sensor Networks
ACM Transactions on the Web
Formal Aspects of Computing
Proceedings of the ACM on Computer Graphics and Interactive Techniques
Proceedings of the ACM on Networking
