In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to…
IEEE Computer Architecture Letters Template
Write in a clean editor, then format for IEEE Computer Architecture Letters in one click — DocuGuru applies the official IEEE template with numbered references and exports a submission-ready PDF plus the editable LaTeX source. Free to start.
About the IEEE Computer Architecture Letters format
IEEE Computer Architecture Letters is a peer-reviewed journal published by IEEE, covering Parallel Computing and Optimization Techniques, Advanced Data Storage Technologies, Interconnection Networks and Systems. Over its lifetime it has published 956 papers, which have received 13,364 citations.
| Publisher | IEEE |
|---|---|
| Reference style | Numbered (IEEE) Numbered — [1], [2] in the text [1] A. Smith, B. Jones, and C. Lee, "A representative article title," IEEE Computer Architecture Letters, vol. 12, no. 3, pp. 45–58, 2023.
Formats any DOI in IEEE Computer Architecture Letters style. No sign-up. |
| Publishes research in | Parallel Computing and Optimization Techniques Advanced Data Storage Technologies Interconnection Networks and Systems Embedded Systems Design Techniques Advanced Memory and Neural Computing |
| ISSN | 1556-6056 |
| Citation impact (2-yr) | 1.43 |
| h-index | 51 |
| i10-index | 285 |
| Top institutions publishing here | Seoul National University |
| Journal website | ieeexplore.ieee.org |
| You get | A submission-ready PDF and the editable LaTeX source — ready to submit. |
Papers published in IEEE Computer Architecture Letters per year
Citation impact of IEEE Computer Architecture Letters by publication year
Citations each year’s papers have accumulated so far — the most recent years are still building up.
Most-cited papers in IEEE Computer Architecture Letters
Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator, a fast and cycle-accurate…
Computer architects must determine how tomost effectively use finite computational resources whenrunning simulations to evaluate new architectural ideas.To facilitate efficient simulations with a range of benchmarkprograms, rn have developed the MinneSPEC inputset for the SPEC CPU 2000 benchmark suite. Thisnew workload allows computer architects to obtain simulationresults in a reasonable time using existing sirnulators.While the…
DRAM technology has developed rapidly in recent years. Several industrial solutions offer 3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the same die. These solutions allow higher density and better performance and also lower power consumption in DRAM designs. However, accurate simulation tools have not kept up with…
gem5-gpu is a new simulator that models tightly integrated CPU-GPU systems. It builds on gem5, a modular full-system CPU simulator, and GPGPUSim, a detailed GPGPU simulator. gem5-gpu routes most memory accesses through Ruby, which is a highly configurable memory system in gem5. By doing this, it is able to simulate many system configurations, ranging from…